| RXFIFO_CNT | (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver’s fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits. |
| ST_URX_OUT | This register stores the value of receiver’s finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1 |
| DSRN | This register stores the level value of the internal uart dsr signal. |
| CTSN | This register stores the level value of the internal uart cts signal. |
| RXD | This register stores the level value of the internal uart rxd signal. |
| TXFIFO_CNT | (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter’s fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits. |
| ST_UTX_OUT | This register stores the value of transmitter’s finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1 |
| DTRN | The register represent the level value of the internal uart dsr signal. |
| RTSN | This register represent the level value of the internal uart cts signal. |
| TXD | This register represent the level value of the internal uart rxd signal. |